OU, CBIT develop ADPLL chip under ‘Chips to Startup’ programme
Osmania University and CBIT have jointly developed and fabricated an all-Digital Phase-Locked Loop (ADPLL) chip under the Chips to Startup (C2S) programme. The 180 nm CMOS chip was unveiled at OU by Vice Chancellor Prof Kumar Molugaram
Hyderabad: In a significant advancement for indigenous semiconductor research, Osmania University (OU), in collaboration with Chaitanya Bharathi Institute of Technology (CBIT), has successfully developed and fabricated a prototype of an all-Digital Phase-Locked Loop (ADPLL) ASIC chip under the Government of India’s Chips to Startup (C2S) programme.
The ADPLL chip, built using 180 nm CMOS technology, was fabricated at the Semiconductor Laboratory (SCL) in Mohali.
OU Vice Chancellor Prof. Kumar Molugaram formally unveiled the chip on Friday in the presence of Academic Council members, university officials, Prof. P. Chandra Sekhar (Principal, UCEOU), and Prof. A. Krishnaiah (Dean, Faculty of Engineering), among others.
Prof. Molugaram lauded the efforts of the project team, led by Prof. P. Chandra Sekhar, for successfully securing the ₹5 crore research grant and for establishing the Centre of Excellence in Artificial Intelligence and Integrated Circuits (CIIC) at OU.
Prof. Chandra Sekhar expressed gratitude to the Ministry of Electronics and Information Technology (MeitY) and CDAC for their continued support, including access to industry-grade Electronic Design Automation (EDA) tools like Cadence and Synopsys, and for facilitating IC fabrication.
The ADPLL chip is expected to play a key role in future applications requiring high-speed digital synchronization, and the achievement marks a step forward for India’s growing semiconductor ecosystem.
